1. Field of the Invention
The subject of the present invention is a data control unit capable of correcting boot errors, and the corresponding self-correction method. In particular, hereinafter the term “data control unit” indicates the control unit forming a board used in devices and apparatuses provided with intelligent functions.
2. Description of the Related Art
As is known and illustrated schematically in FIG. 1, a control unit 1 is typically made up of a central processing unit (CPU, 2); a nonvolatile memory 3; and a volatile random-access memory (RAM, 4). The CPU 2 works according to an operating system (OS) that is stored in a nonvolatile way in the nonvolatile memory 3 and is loaded into the RAM 4 (preferably a SRAM) upon turning-on of the control unit 1.
In detail, the modalities of turning-on are described hereinafter. Upon power-up of the device or apparatus incorporating the data control unit, when power is supplied, a reset signal is generated, which activates switching of all the components (latches, flip-flops, registers, etc.) from an unknown state to a known state. Furthermore, the reset signal determines addressing, within the nonvolatile memory 3, of a vector (called reset vector) containing the value of a pointer to a reset-service routine, which is also stored in the nonvolatile memory 3. The address of the reset vector is fixed and is usually mapped on the first address (00 . . . 00 hexadecimal) or on the last address (FF . . . FF hexadecimal), for reasons of simplicity.
Next, the reset-service routine is executed, which initializes the CPU 2 and activates a boot routine (which is also stored in the nonvolatile memory 3). In turn, the boot routine resets the state of all the components (for example, for executing a power-on-self test (POST) and loads the code of the operating system as well as the drivers from the nonvolatile memory 3 into the RAM 4.
Once the operating system is loaded into the RAM 4, it assumes the control over the entire control unit 1.
The nonvolatile memory 3 may, for example, be a flash memory of a NOR type or, a NAND type, or a ROM.
Currently on the market there is an increasing use of flash memories of a NAND type since they offer an economic answer, as compared to flash memories of a NOR type, to the requests for high density of data and code storage. They find, in particular, advantageous application in multimedia systems, such as web browsing, video streaming, GPS services, recording of images, games, MP3 reproduction, etc.
In particular, NAND flash memories ensure high performance during programming, sequential erasing and reading, thanks to their internal paged architecture, even though they require an external RAM for executing bootstrapping.
Furthermore, NAND flash memories are structured so as to automatically download the contents of the page “0” upon power-up, without the need for an appropriate read command to be generated.
In fact, as soon as the supply voltage exceeds a threshold voltage such as to guarantee execution of the normal operations, the page 0 is retrieved and copied into a buffer.
The boot operations occur normally according to two modalities: a boot-loader method and a boot-engine method.
In the first case, the boot-loader method (see also FIG. 2), the nonvolatile memory comprises two parts: a ROM 10, of small dimensions (e.g., approximately 20 KB), which stores the reset vector and the boot loader, and a NAND 11, of larger dimensions, which stores the operating code and the application data. Generally, the ROM 10 is made in a same device integrated with the CPU 12, for example a microcontroller; the RAM 13 here is preferably a DRAM so as to be able to satisfy the requirements of density existing in multimedia systems.
In the second case, the boot-engine method (see FIG. 3), a hardware circuit is provided (called boot engine, designated by 15), which controls the bootstrapping operations. The boot engine 15 can be integrated with the CPU 16 to form a microcontroller, as represented by the dashed block, or else may be an external component or again be integrated with the NAND 17. Specifically, the boot engine 15 comprises an executive portion (“download engine”) and a temporary memory portion (“boot buffer”), while the NAND 17 stores the reset vector, the boot code, and the operating system.
Initialization of the control unit is described hereinafter. Upon receipt of the reset signal, the boot engine 15 freezes the CPU 16; then, it downloads the reset vector and the boot code from the NAND 17 and stores them in its boot buffer. Next, the boot engine 15 awakes the CPU 16, which executes the boot code and downloads the operating code into the RAM 18 (also here, a DRAM).
Both of the methods described above (boot-loader method and boot-engine method) are affected by reliability problems, due to bad memory blocks. Already when they leave the factory, a small percentage of blocks can be non-functioning; in this case, they are marked as “bad blocks” and are no longer available for use. During the life of the control unit, other blocks can go bad; consequently, the system comprises a software module (called bad-block manager), which highlights the onset of a failure and keeps a table of the unusable blocks updated. This routine cannot, however, work on the block 0 since it is not yet active during bootstrapping.
Because of the extreme importance of the block 0 for execution of the bootstrapping operation, as described above, only memories that have a functioning block 0 are put on the market, but there is no way of guaranteeing that this will remain so throughout the life of the control unit. On the other hand, the failure of even just one bit of the block 0 can bring about crashing of the entire system.
Consequently, the need exists of ensuring, on the one hand, that the data read are correct, and on the other, that the data control unit is able to function even when the block 0 containing the boot code is bad.
Currently, in general, nonvolatile memories, in particular NAND flash memories, require an algorithm for correcting errors, called error-correction code (ECC), which is able to correct a certain number of errors. The exact number of errors that can be corrected in the individual cases is determined according to the statistical knowledge of the susceptibility of the memory to errors. For example, typical ECC systems for current NAND memories are able to correct up to three errors. To do this, added to each datum is redundant information such as to enable not only the detection of the presence of errors, but also their correction and the reconstruction of the original correct datum. However, even this algorithm cannot act on the block 0 during bootstrapping and hence cannot guarantee the functionality of said block for the entire life of the control unit.